Implementation of Optimized 128-point Pipeline Fft Processor Using Mixed Radix 4-2 for Ofdm Applications

Abstract This paper proposes a 128-point FFT processor for Orthogonal Frequency Division Multiplexing (OFDM) systems to process the real time high speed data based on cached-memory architecture (CMA) with the resource Mixed Radix 4-2 algorithm using MDC style. The design and implementation of FFT processor has been done using the above technique to reduce the size and power. Using the above algorithm the chip size will be 2.8 x 2.8 mm with 0.35μm technology. The power consumption with our optimum case is 72 mW for an operating speed of 127-133 MHz which is only less than half of the latest reported 128-Point FFT design with 0.18 um technology. A comparison has been made for various pipeline architectures such as MDC, SDF, and SDC using the same algorithm for the design of 128-point FFT processor with respect to memory size, area and power.